********* -top view- 1 2 3 4 5 6 7 8 9 10 av cc 12 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 dgnd cc dv dv ee pin no. i/o signal pin no. i/o signal pin no. i/o signal pin no. i/o signal 1 2 3 4 5 6 7 8 9 10 11 12 - 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 vc fgd fs3 flb feo fe- srch tgu tg2 tao ta- sl+ slo sl- fset iset sstop dirc clk xlt data xrst c.out dgnd av cc av ee dv ee ee - i i i i o i i i i o i i o i i i i i i i i i i o i i i i i CXA1082BQ(1/3) o sens bw i i pdi vcof i 3.5v o c864 o lock i mdp i i i mon fsw dv cc spdl- o spdlo i wdck fok i mirr dfct ite i i atsc ife il08 (+5v) (-5v) (+5v) av (-5v) tzc servo signal processor for cd
i l data register 2 input shift register address decoder sequencer output decoder vco 3.5v regulator vi loop filter clv lpf tracking tm6 tm5 tm3 tm4 ttl i l 2 ttl i l 2 bpf window comparator compensation phase focus phase compensation fs1-4 tg1-2 tm1-7 ps1-3 34 35 36 38 27 29 28 30 16 33 25 24 23 22 21 40 41 42 44 46 47 12 13 15 45 3 48 2 4 6 7 39 14 11 5 mdp mon fsw spdl- bw iset pdi vcof sstop lock clk xlt data xrst dirc wdck fok mirr dfct tzc atsc ta- sl+ sl- te fs3 fe fgd flb fe- srch slo tao feo 31 32 3.5v c864 i l 2 ttl 20 18 c.out sens 1 vc 8 tgu 9 tg2 10 cc av 17 fset 19 ee av 26 dgnd spdlo 37 43 cc dv ee dv CXA1082BQ(2/3)
34 35 36 38 27 29 28 30 16 33 25 24 23 22 21 40 41 42 44 46 47 12 13 15 45 3 48 2 4 6 7 mdp mon fsw spdl- bw iset pdi vcof sstop lock clk xlt data xrst dirc wdck fok mirr dfct tzc atsc ta- sl+ sl- te fs3 fe fgd flb fe- srch 8 tgu 9 tg2 17 fset 39 14 11 5 slo tao feo 31 32 3.5v c864 20 18 c.out sens spdlo CXA1082BQ(3/3) input fgd fs3 flb feo tao fe- srch tgu tg2 ta- sl+ sl- fset iset sstop dirc lock clk xlt data xrst sens c.out mirr dfct tzc te fe output ;serial data transfer clock input from cpu. ;serial data input from cpu. ;connect a capacitor between this pin and pin 3 to reduce high-frequency gain. ;time constant external pin to raise the low bandwidth of the focus servo. servo is switched through fs3 on and off. ;the high-frequency gain of the focus phase compensation and fc of clv lpf. ;current is input to determine focus search, track jump,and sled kick height. ;at l sled runaway prevention circuit operates. ;non-inverse input pin for sled amplifier. ;inverse input pin for sled amplifier. ;time constant external pin for the formation of focus search waveforms. ;limit sw on/off signal detection pin for disc inner periphery detection. ;inverse input pin for tracking amplifier. the selection of tracking high band gain. ;time constant external pin for ;time constant external pin for the selection of tracking high band gain. ;latch input from cpu. ;reset input pin,reset at l atsc ;track number count signal output. ;focus drive output. ;sled drive output. ;tracking drive output. ;window comparator input pin for atsc detection. ;inverse input pin for focus amplifier. ;pin to set peak frequency of focus tracking bw ;time constant external pin for loop filter. fok fsw mdp mon pdi vcof wdck c864 slo spdl ;pin for one-track jump. ;input for focus error. ;time constant external pin for clv servo error signal ;inverse input for spindle drive amp. ;mdp signal input. ;mon signal input. ;pdo signal input. ;focus ok signal input. ;input for tracking zero-cross comparator. ;clock input for auto. ;8.64mhz vco output ;defect signal input. ;mirr signal input. ;outputs fzc,as,tzc,sstop and busy through command from cpu. ;spindle drive output. spdl- ;tracking error signal input. ;vco frequency control.
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